In the fabrication of semiconductor devices, there is relentless pressure to miniaturize components to achieve higher circuit density on a single semiconductor chip and to increase semiconductor device speed and reliability, lower energy usage, and provide better portability of the semiconductor devices. In this way, electronic equipment becomes smaller and more reliable, assembly and packaging costs are minimized, and integrated circuit (“IC”) performance is improved. However, as components become smaller and are packed closer together, leakage and second order effects of the semiconductor device become significant.
One semiconductor device that is subject to the pressure to miniaturize is the dynamic random access memory (“DRAM”). DRAMs include arrays of memory cells, each of which includes a field effect access transistor and a capacitor. Typically, a first side of the field effect access transistor is connected to a first side of the capacitor. A second side of the field effect access transistor and a transistor gate electrode are connected to connection lines of the array called a bit line and a word line, respectively. The second side of the capacitor is connected to a reference voltage. Therefore, forming the DRAM memory cell includes forming the field effect access transistor, the capacitor, and contacts to external circuits. The DRAM memory cell conventionally includes one metal oxide semiconductor (“MOS”) transistor and one capacitor within a semiconductor substrate on which a plurality of spaced gates (word lines) and a plurality of spaced metal traces (bit lines) are aligned perpendicular to each other in widthwise and lengthwise directions. Additionally, one active area having two gates, two capacitors and one bit contact are conventional on DRAM. The areas in a DRAM to which electrical connections are made are referred to as active areas. Active areas, which serve as source and drain regions for transistors, are discrete, specially doped regions in the surface of the semiconductor substrate.
Various conventional wet etch chemistries have been used to etch silicon, such as a silicon semiconductor substrate. For example, both single crystalline and polycrystalline silicon have been wet etched using a mixture of nitric acid (“HNO3”) and hydrofluoric acid (“HF”). Such etchants generally provide isotropic etching. The etching is initiated by the HNO3, which forms a layer of silicon dioxide on the silicon, while the HF dissolves the silicon dioxide. In some cases, water is used to dilute the etchant, with acetic acid (“CH3COOH”) being a preferred buffering agent, since the CH3COOH causes less disassociation of HNTO3 and yields a higher concentration of the disassociated species. The ratio of HNO3, HF, and CH3COOH is adjusted as necessary to yield different etch rates.
In some applications, it is useful to etch silicon more rapidly along one crystalline plane compared to another crystalline plane. For example, in the diamond lattice of silicon, the (111) plane is more densely packed than the (100) plane. Thus, the etch rate of (111) silicon is expected to be lower than silicon in the (100) plane. One etchant that exhibits such orientation-dependent etching includes a solution of potassium hydroxide (“KOH”) and isopropyl alcohol. This solution etches silicon about one hundred times faster along (100) planes than along (111) planes. Conventional IC processing for DRAM semiconductor devices, other memory semiconductor devices, and microprocessors, etc. is currently performed on silicon monocrystalline sliced on a (100) plane and oriented in a <110> direction. The plane and direction of the silicon are determined by a notch in the semiconductor substrate, as known in the art. However, current techniques for wet etching silicon do not always create the structures desired with the desired geometries and density with (100) silicon. Potassium hydroxide and tetramethyl ammonium hydroxide (“TMAH”) are used to create vertical etches in (110) silicon by using a (110) semiconductor substrate or causing the recrystallization of the surface of a semiconductor substrate to produce a (110) crystal orientation. However, transistor properties are fastest on (100) silicon because this plane of silicon gives MOS devices the highest electron mobility. Most CMOS and DRAM devices are optimized for these types of wafers.
Recently, new techniques for forming a single crystalline silicon layer on an insulation layer, which is referred to in the art as silicon-on-insulator (“SOI”), and of integrating unit-devices on the silicon layer have been developed. In fabricating a semiconductor device using a SOI structure, a junction capacitance in driving the semiconductor device is lowered, thus improving the speed compared to a general bulk device. SOI structures may be used to provide semiconductor devices having a smaller junction area, simple isolation structure, and steeper subthreshold-voltage slopes. In a SOI structure, a silicon substrate and a silicon upper layer part are separated by a field oxide film within an SOI layer and by an insulation layer, such as a buried oxide (“BOX”) layer separating the silicon upper layer part from the silicon substrate. Additionally, there is an active area sealed by the BOX layer and the field oxide film is used as a channel area of a transistor. However, the BOX layer prevents potential lines spreading into the silicon substrate, and also is a poor conductor of heat, which results in SOI power devices having greater self-heating and poorer breakdown characteristics when compared to junction isolated counterparts.
To reduce these problems, pseudo silicon-on-insulator (“PSOI”) structures have been developed. PSOI structures are reported to improve DRAM leakage current by as much as 30%, which characteristic is highly desirable for DRAM manufacturing and semiconductor device performance. Some PSO structures employ a semiconductor substrate having windows etched into the BOX layer, the windows then being refilled with silicon. The windows and silicon fill enable heat generated by the semiconductor device to dissipate more rapidly into the semiconductor substrate and also enable potential lines to spread into the semiconductor substrate, improving the breakdown voltage of the power devices. However, fabricating these PSOI structures provides some technological challenges and is expensive.
It would be desirable to provide an inexpensive method of fabricating PSOI structures for use in semiconductor memory devices, as well as in other, semiconductor non-memory devices.